Compared with linear regulators, switching mode power supplies have the advantages of smaller size higher efficiency and larger output power capability.
Pulse Width Modulation (PWM) is one of major control architectures applied in switching mode power supplies. Emitter drive PWM control has the advantage of fewer pin counts compared with base drive PWM control.
FIG. 1 is an emitter drive switching mode power supply system which includes an emitter drive PWM controller coupled with a primary winding of the transformer through a high voltage NPN power transistor. Energy is transferred to secondary winding from the primary winding in a manner controlled by the PWM controller to provide a constant DC output voltage. The auxiliary winding is coupled with an opto-coupler which provides a bias signal and feedback signal to the PWM controller.
In FIG. 1, the system comprises a PWM controller 100, transformer 102, power transistor 124, shunt voltage regulator 121, opto-coupler 101 and feedback loop composed of 108, 109, 117, 121, 110, 112 and 113.
The PWM controller 100 drives power transistor 124. When Vout rises, the opto-coupler 101 will deliver more current to the capacitors associated with the VCC/FB pin of the PWM controller 100, so as to reduce the duty cycle and the energy transferring to the secondary side to stabilize the Vout.
FIG. 2 is the block diagram of the PWM controller of the prior art. The PWM controller 200 comprises a start-up circuit 201 which is connected between the supply/feedback pin VCC and emitter drive pin OUT. The PWM controller 200 also comprises a hysteresis UVLO comparator 203. During startup phase, capacitors connected to VCC pin are charged by the startup current from OUT pin through start-up circuit 201. The UVLO comparator 203 ends the startup phase by disconnecting the charging path between OUT and VCC and enable the HICCUP comparator 213 when VCC voltage exceeds the upper triggering voltage of the UVLO comparator.
After the start-up phase, the PWM controller 200 starts to operate and VCC pin also receives voltage feedback signal. When Vout falls due to output load current increase, opto-current decreases, VCC/FB voltage will decrease, the duty cycle will increase. When Vcc falls below the lower triggering voltage of the UVLO comparator 203, PWM controller 200 will disable the switching of the power transistor 124 and enable the startup circuit 201. The system reenters the startup phase.
The PWM controller 200 also comprises a peak current comparator 210 which will compare internal current in each switch cycle.
The PWM comparator 205 will adjust the duty cycle according to the feedback voltage and emitter current signals.
The OUT pin will drive the power transistor 124 with varied duty cycle according to the output of PWM comparator 205.
In switching mode power supplies, the function of limiting both instantaneous and average input power is essential during short circuit operation for system reliability. In the prior art of FIG. 1, input power limiting during short circuit operation is implemented by monitoring the voltage at OUT pin when power transistor 124 is off. The resistor divider 212 and HICCUP comparator 213 will detect the OUT voltage during power transistor 124 off time. In the case that the OUT voltage drops below a pre-defined low value (HICCUP voltage) before Vcc drops below to its minimum operating voltage (lower UVLO voltage), the HICCUP comparator 213 will output a low voltage level to disable the PWM comparator 205, thus disables the drive circuit and the whole PWM controller 200. The system will then enter into repeated startup phase. This is called a hiccup mode of the system and the pre-defined voltage of OUT pin is called the HICCUP voltage of the system. The VCC/FB and OUT waveforms in HICCUP mode are illustrated in FIG. 3.
The VCC and OUT waveforms without HICCUP mode are illustrated in FIG. 4.
In either case of FIG. 3 and FIG. 4, the instantaneous system input power is determined by the maximum turn-on time of the PWM pulses. The average system input power is determined by the total turn-on pulses and the charging time of the VCC cap 113 and 112 to the upper UVLO triggering voltage level.
The charging time of the VCC capacitor 113 and 112 to the upper UVLO voltage level is a function of the initial voltage of capacitor 111 when the VCC drops below the lower UVLO voltage level or the OUT pin drops below the HICCUP voltage. In application systems, the coupling among the primary, secondary and auxiliary windings will determine the initial voltage of capacitor 111 when the VCC drops below UVLO voltage or the OUT pin drops below the HICCUP voltage. The VCC restart-up frequency will speed-up for some kind of transformers with higher voltage of capacitor 111. The average short circuit input power will then increase. Especially, when the input line voltage is high, the short circuit power will be larger in the prior art for some kind of transformer design. It may cause PWM controller 200 or power transistor 124 or other device failure and degrade system reliability.
Accordingly, what is needed in the present invention is a PWM controller 200 with both instantaneous and average short circuit input power limiting functions which are transformer insensitive so as to improve system reliability.
This short circuit protection mechanism of the prior art is based upon the hypothesis that the auxiliary winding has good coupling with the secondary winding of transformer. If the coupling between auxiliary winding and secondary winding is not very well, the OUT pin may not drop below the HICCUP voltage during short circuit operation. In this case, VCC voltage will continue to drop until it reaches the lower voltage level of UVLO comparator. The instantaneous system input power will be significantly larger than the case in normal operations because the lower voltage level of the UVLO voltage may be significantly lower than the mean VCC voltage under the condition of maximum output current and normal output voltage. The average system input power will be determined by the mean input power in startup phase multiplied by Ton/(Ton+Toff), where Ton is the time when UVLO comparator outputs high voltage level, and Toff is the time the UVLO comparator outputs low voltage level.